A typical computer system includes a processor, memory (e.g., semiconductor memory, disk drive memory, etc.) and a bus that connects the processor to the memory. The bus typically includes control lines, address lines and data lines. During normal operation, the processor places a command on the control lines and an address on the address lines in order to access a particular location within the memory. If the command is a read instruction, the memory responds by placing data (e.g., general data, executable code, etc.) onto the data lines from the particular location of the memory and the processor subsequently reads that data from the data lines. If the command is a write instruction, the processor places data onto the data lines and the memory responds by storing the data in the particular location of the memory.
Before the processor begins normal operation, the processor typically performs a startup sequence (i.e., a series of routines) in order to initialize internal circuitry and output lines, as well as to reach a steady and consistent operating state. It is common for the processor to perform this startup sequence in response to a special event such as immediately after powering up, after receiving a reset signal, and after encountering an exception or fault event (e.g., a branch into an error condition). If the processor does not perform the startup sequence following such an event, the operating state and the output signals of the processor will be unreliable.
In general, when the processor performs the startup sequence, the processor executes special code called firmware stored in Programmable Read Only Memory (PROM). The processor typically retrieves this firmware from a base region of the PROM by (i) asserting command and address lines and (ii) reading data lines in a manner similar to that described above for accessing primary and secondary memory during normal operation. Manufacturers of computer systems often store other memory constructs in the firmware within the PROM as well, such as routines for handling various traps and software conditions, update and diagnostic routines, etc.
In some situations, subsequent versions of the firmware may outgrow the native memory capacity of the processor, i.e., the memory space which is addressable using only the standard address lines of the processor. For example, for a particular computer system design, suppose that a processor has exactly 20 standard address lines and thus is capable of addressing one megabyte of native memory space (i.e., 2^2 bytes of memory). In such a situation, if the firmware fits within one megabyte of memory space, the processor is capable of addressing all of the firmware using the 20 standard address lines. However, if the firmware is larger than one megabyte of memory space (i.e., if the firmware exceeds the native memory capacity of the processor), the manufacturer must then provide a mechanism that enables the processor to access a memory space which is larger than the processor's native memory capacity so that the processor has access to all of the firmware.
There are a variety of conventional approaches to modifying a computer system design to expand the size of addressable memory space beyond the processor's initial native memory capacity. One conventional approach to modifying the computer system design (which is hereinafter referred to as the “new processor approach”) involves replacing the processor of the initial design with a new processor having more standard address lines and thus greater addressing capabilities. Accordingly, in this approach, the manufacturer essentially increases the native memory capacity beyond the initial native memory capacity.
Another conventional approach to modifying a computer system design to expand the size of addressable memory space beyond the processor's initial native memory capacity (which is hereinafter referred to as the “simple GPIO line approach”) involves utilizing general purpose input/output lines (i.e., GPIO lines) of the processor as additional address lines. In this approach, the manufacturer provides code (e.g., an application) which directs the processor to operate the GPIO lines as higher order address lines, i.e., as address lines carrying the most significant address bits. This approach places the GPIO lines of the processor under software control so that the GPIO lines, in combination with the standard address lines of the processor, provide addresses for addressing a memory space that is larger than the native memory capacity of the processor.